1. Technical Field
The present invention relates to the manufacturing method for a semiconductor device, a semiconductor device, a circuit substrate and an electronic device.
2. Related Art
In recent years, there has been a demand to miniaturize and reduce the weight of portable telephone devices, notebook portable computers and portable electronic devices such as a PDA (personal digital assistant) and the similar.
Accompanying the demand for miniaturization and weight reduction, there has also been demand to limit the packaging space for each type of electronic product, such as semiconductor devices and the similar, provided within the electronic devices, as well as to miniaturize packaged electronic products.
Given this background, in order to accomplish the corresponding to the miniaturization of electronic products, high-density packaging (three-dimensional packaging) which accomplishes multi-layering of semiconductor devices, as well as the thinning processing of the electronic products themselves has been widely performed.
Generally, in thinning the semiconductor devices, as back grind processing, semiconductor wafers have been thinned by grinding and polishing the reverse side surface (rear surface) of the semiconductor wafer circuit forming surface.
Subsequently, during dicing processing, a plurality of thinned semiconductor devices can be manufactured by dividing semiconductor wafers for each semiconductor region formed on the semiconductor wafer circuit forming surface.
However, in the above described manufacturing method, damaged layers having minute fissures (cracks) are formed on the rear surface of the semiconductor wafer, caused by back grind processing.
Furthermore, there has been the problem in that, if the semiconductor rear surface damaged layer is left in its existent state, and if the manufacturing of the semiconductor device is continued, beginning with cracking of the damaged layer, the semiconductor element becomes completely broken.
Furthermore, there has been the problem in that, during dicing processing, in order to mechanically remove the semiconductor wafer by bevel cutting and the similar, minute cracking and chipping and the similar has been generated in the area of the cut surface of the semiconductor wafer.
In addition, since the semiconductor wafer is thin, there has been the problem of excessive stress on the portions in which cracking, chipping and the similar are generated.
In order to resolve the generation of such problems during the back grinding and dicing processes, the following methods are proposed.
(1) With the method disclosed in Japanese Unexamined Patent Application First Publication No. 2000-228389, in a state in which a tape member pasted to the surface of a wafer on which a circuit is formed, the rear surface of the wafer is polished, and wafer thinning is performed by plasma etching the rear surface of the polished wafer.
According to this method, the damaged layer can be removed by wet etching the rear surface of the wafer.
(2) With the method disclosed in Japanese Unexamined Patent Application First Publication No. 2002-93752, after testing the semiconductor wafer, attaching dicing tape to the rear surface of the semiconductor wafer via a carrier frame, and accomplishing semi-full dicing from the element forming surface on the semiconductor wafer, the dicing tape is exfoliated.
Continuing, after attaching etching resistant film to the element forming surface of the semiconductor wafer via the carrier frame, the semiconductor wafer is immersed in an etching solution, and the semiconductor wafer thinning is executed.
According to this method, the polishing of semiconductor wafer rear surfaces, the forming of the piece semiconductor devices by dividing the semiconductor wafers, and the removing of the affected and damaged layers (damaged regions) generated on the cut surface by semi-full dicing processing can be simultaneously performed.
However, in the above disclosed method, there are the following problems.
(1) In the method disclosed in Unexamined Japanese Unexamined Patent Application First Publication No. 2000-228389, there has been the problem in that, order to remove the damaged layer formed on the semiconductor wafer rear surface by grinding and polishing through plasma etching, a longer time is required than with other etching methods.
(2) In the method disclosed in Japanese Unexamined Patent Application First Publication No. 2002-93752, there has been difficulty in handling the wafer to accomplish semi (full) dicing after thin processing the semiconductor wafer.
(3) Furthermore, in the above described method, when thinning the semiconductor device, stress easily concentrates in end portions of the semiconductor device, and the semiconductor device is damaged and broken.